In integrated circuits, logic signals must arrive at an appropriate time to be properly read. This requires that the logic signals must be properly timed with respect to pulses that initiate transferring the signals such as to or from a bus. Prior to being placed on a bus, the logic signals may be buffered to assure being placed on the bus at the appropriate time. When the buffer is strobed to initiate data transfer, the switching speed of logic devices in the signal path contribute to a propagation delay. One problem is that the propagation delay may vary over a relatively large range due to variations in operating conditions such as effects of temperature, supply voltage, and device parameter variations during manufacture of the integrated circuit.
One solution has been to add a fixed time delay component to the buffer such that the total propagation delay falls within the desired time range. While this solution will suffice in some applications, it is not adequate for all applications.
Another solution uses feedback in the form of a phase or delay locked loop to adjust the propagation delay of a circuit to track the period of a reference clock. The disadvantage of this solution is the need for the feedback control loop and reference clock.
U.S. Pat. No. 4,791,326 discloses another solution in which switching characteristics of a transistor are maintained nearly uniform as circuit and process variations cause switching conditions to change. A compensated current source controls the peak switching current through a switching transistor to be fairly constant under all switching conditions to control the switching transition time (propagation delay) introduced by the transistor. The switching characteristics are maintained nearly uniform as circuit and process variations cause switching conditions to change, resulting in a nearly uniform propagation delay. However, this approach suffers from the drawback that the compensation circuit does not sense all of the circuit conditions and process speed variations that influence propagation delay.
An improved propagation delay compensation technique is desired that senses the circuit conditions and process speed variations that influence propagation delay in a signal path switching device and provides a control signal incorporating effects of the sensed parameters, such as in the form of a bias current, to produce a variable delay with the result that the total propagation delay in the signal path is controlled to be within an acceptable, predetermined range.